View PS501-ISS_1674526.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2004 microchip technology inc. ds21818b-page 1 ps501 features ? single chip solution for rechargeable battery management footprint compatible with ps401 smbus 1.1 and sbdata 1.1 compatible precise capacity reporting for lithium ion and lithium polymer battery chemistries embedded powersmart ? patented algorithms contained in customizable on-chip 16-kbyte flash memory user configurable and ?learned? parameters stored in on-chip 256 x 8 eeprom algorithms and parameters fully field reprogrammable via smbus interface integrating sigma-delta a/d converter with 9 to 16-bit programmable resolution which accurately measures: - current through sense resistor - high-voltage (18v) battery cells directly connected to v cell inputs - temperature measurement from on-chip sensor or optional external thermistor integrated precision silicon time base twelve individually programmable input/output pins that can be assigned as charge control i/o, secondary safety function i/o, soc led output or general purpose i/o - two of the twelve i/os are high voltage, capable for direct drive of charge and safety fets on-chip regulator generates precision digital and analog supply voltages directly from pack voltage supports direct connection to 2 to 4-cell lithium packs flexible power operating modes: - run: continuous operation - sample: periodic measurements at programmable intervals - sleep: shutdown mode due to low voltage. power consumption less than 25 a. - shelf-sleep: shuts off ps501 power consumption for pack storage with automatic wake-up on pack insertion. power consumption is less than 1 a. integrated reset control - power-on reset - watchdog timer reset - brown-out detection reset pin description pin summary pin name type description v ddd , v ssd supply digital supply voltage input, ground gpio(0..9) i/o programmable digital i/o gpiohv1,2 i/o open-drain programmable digital i/o for direct drive of fets mclr i master clear. pull-up in normal operation smb-clk, smb-dta i/o smbus interface vc(1..4) i cell voltage inputs v dda , v ssa supply voltage regulator output (internally connected to analog supply input), ground rshp, rshn i current sense resistor input v ntc i external thermistor input v reft o thermistor reference voltage r osc i internal oscillator bias resistor v ddd gpio(4) gpio(5) gpio(6) gpio(7) smb-clk smb-dta vc(4) vc(3) vc(2) vc(1) v dda v ssa rshp v ssd gpio(3) gpio(2) gpio(1) gpio(0) gpiohv2 mclr gpiohv1 gpio(9) gpio(8) r osc v reft v ntc rshn ps501 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28-pin ssop package - 209 mil single chip field reprogrammable battery manager
ps501 ds21818b-page 2 ? 2004 microchip technology inc. 1.0 product overview the ps501 combines a high-performance, low-power microchip pic18 microcontroller core together with powersmart proprietary monitoring/control algorithms and 3d cell models stored in 16 kbytes of on-chip reprogrammable flash memory. analog resources include a 16-bit sigma-delta integrat- ing a/d and mixed signal circuitry for precision measurement of battery current, temperature and volt- age and for direct connection to 4-cell series lithium ion packs. on-chip eeprom is provided for storage of user customizable and ?learned? battery parameters. an industry standard 2-wire smbus interface supports host communication using standard sbdata commands and status. additional integrated features include a high accuracy on-chip oscillator and temperature sensor. twelve gen- eral purpose pins support charge or safety control or user programmable digital i/o. eight of them can be used as led drivers and two are open drain for direct fet drive. the ps501 can be configured to accommodate all lithium rechargeable battery chemistries, including li ion graphite, li ion hard carbon and li ion polymer, with direct connection to 2 to 4 series cell configurations. figure 1-1: ps501 in ternal block diagram 256-byte eeprom 256-byte eeprom 16-kbyte flash 16-kbyte flash decoder regulator regulator voltage reference and temperature sensor voltage reference and temperature sensor smbus interface smbus interface pic18 microcontroller core pic18 microcontroller core 16-bit sigma-delta integrating a/d converter 16-bit sigma-delta integrating a/d converter analog input mux analog input mux programmable digital input/output programmable digital input/output silicon oscillator silicon oscillator r osc smb-clk rshn v ntc v dda 1 2 v reft 3 v ddd smb-dta v ssd gpio(11-0) digital section analog section v ssa rshp vc(2-4) vc(1)
? 2004 microchip technology inc. ds21818b-page 3 ps501 1.1 architectural description the ps501 is a a fully field reprogrammable single chip solution for rechargeable battery management. figure 1-1 is an internal block diagram highlighting the major architectural elements described below. 1.2 microcontroller/memory the ps501 incorporates an advanced, low-power microchip pic18 8-bit risc microcontroller core. mem- ory resources include 16 kbytes of reprogrammable flash memory for program/data storage and 256 bytes of eeprom for parameter storage. both memory arrays may be reprogrammed through the smbus interface. 1.3 a/d converter the ps501 performs precise measurements of current, voltage and temperature, using a highly accurate 16-bit integrating sigma-delta a/d converter. the a/d can be calibrated to eliminate gain and offset errors and incor- porates an auto-zero offset correction feature that can be performed while in the end system application. 1.4 powersmart ? firmware/battery models contained within the 16-kbyte flash memory is the powersmart developed battery management firmware that incorporates proprietary algorithms and sophisti- cated 3-dimensional cell models. developed by battery chemists, the patented, self-learning 3d cell models contain over 250 parameters and compensate for self- discharge, temperature and other factors. in addition, multiple capacity correction and error reducing func- tions are performed during charge/discharge cycles to enhance accuracy and improve fuel gauge and charge control performance. as a result, accurate battery capacity reporting and run-time predictions with less than 1% error are achievable. the reprogrammability of the flash allows firmware upgrades and customized versions to be rapidly created without the need for silicon revisions. the ps501 can be easily customized for a particular application?s battery cell chemistry. standard configura- tion files are provided by powersmart for a wide variety of popular rechargeable cells and battery pack configurations. 1.5 smbus interface/sbdata commands communication with the host is fully compliant with the industry standard smart battery system (sbs) specification. included is an advanced smbus commu- nications engine that is compliant with the smbus v1.1 protocols. the integrated firmware processes all the revised smart battery data (sbdata) v1.1 values. 1.6 accurate integrated time base the ps501 integrates a highly accurate silicon oscilla- tor that provides accurate timing for self-discharge and capacity calculations and eliminates the need for an external crystal. 1.7 temperature sensing an integrated temperature sensor is provided to minimize component count when the ps501 ic is located in close physical proximity to the battery cells being monitored. as an option, a connection is provided for an external thermistor that can also be monitored. 1.8 general purpose i/o twelve programmable digital input/output pins are pro- vided by the ps501. eight of these pins can be used as led outputs to display state-of-charge (soc), used for direct control of external charge circuitry or to pro- vide additional levels of safety in li ion packs. alterna- tively, they can be used as general purpose input/ outputs. two of the i/os are open-drain outputs and can thus be used to directly drive fets or other high- voltage applications.
ps501 ds21818b-page 4 ? 2004 microchip technology inc. table 1-1: pin descriptions pin name description 1v ddd (input) filter capacitor input for digital supply voltage. 2 gpio(4) (bidirectional) programmable general purpos e digital input/output pin (4) or led driver. 3 gpio(5) (bidirectional) programmable general purpos e digital input/output pin (5) or led driver. 4 gpio(6) (bidirectional) programmable general purpos e digital input/output pin (6) or led driver. 5 gpio(7) (bidirectional) programmable general purpos e digital input/output pin (7) or led driver. 6 smb-clk smbus clock pin connection. 7 smb-dta smbus data pin connection. 8 vc(4) (input) cell voltage input for the fourth highest voltage cell in a series string. 9 vc(3) (input) cell voltage input for the third highest voltage cell in a series string. 10 vc(2) (input) cell voltage input for the second highest voltage cell in a series string. 11 vc(1) (input) cell voltage input for the first or highest voltage cell in a series string. 12 v dda (input) analog supply voltage input. 13 v ssa analog ground reference point. 14 rshp (input) current measurement a/d input from positive side of the current sense resistor. 15 rshn (input) current measurement a/d input from negative side of the current sense resistor. 16 v ntc (input) a/d input for use with an external temperature circuit. this is the midpoint connection of a voltage divider, where the upper leg is a thermistor (103etb type) and the lower leg is a 3.65 kohm resistor. this input should not go above 150 mv. 17 v reft (output) reference voltage output for use with temperature measuring a/d circuit. this 150 mv output is the top leg of the voltage divider and connects to an external thermistor. 18 r osc external bias resistor. 19 gpio(8) (bidirectional) programmable general purpose digital input/output pin (8). 20 gpio(9) (bidirectional) programmable general purpose digital input/output pin (9). 21 gpiohv1 (bidirectional) programmable general purpose digital input/output pin (10). open-drain, high-voltage tolerant. 22 mclr (input) master clear. must be pulled up for normal operation. 23 gpiohv2 (bidirectional) programmable general purpose digital input/output pin (12). open-drain, high-voltage tolerant. 24 gpio(0) (bidirectional) programmable general purpose digital input/output pin (0) or led driver. 25 gpio(1) (bidirectional) programmable general purpose digital input/output pin (1) or led driver. 26 gpio(2) (bidirectional) programmable general purpose digital input/output pin (2) or led driver. 27 gpio(3) (bidirectional) programmable general purpose digital input/output pin (3) or led driver. 28 v ssd digital ground reference point.
? 2004 microchip technology inc. ds21818b-page 5 ps501 2.0 a/d operation the ps501 a/d converter measures current, voltage and temperature and integrates the current over time to predict state-of-charge. pack voltage and individual cell voltages are monitored and can be individually cal- ibrated for the best accuracy. using an external sense resistor, current is monitored during both charge and discharge and is integrated over time using the on-chip oscillator as the time base. temperature is measured from the on-chip temperature sensor or an optional external thermistor. current and temperature are also calibrated for accuracy. 2.1 a/d converter list the a/d converter alternately measures pack voltage, cell voltages, current, temperature and auto-offset as explained below. the schedule for the sequence and frequency of these measurements is programmable, as is the number of bits used. the default scheduling uses three lists. at near full (above the voltage point adlnearfull ) and near empty (below the voltage point adlnearempty ), voltage intensive lists are used to accurately end charge or discharge. in between adlnearfull and adlnearempty , a current intensive schedule is used to more accurately calculate capacity. 2.2 current measurement the a/d input channels for current measurement are the rshp and rshn pins. the current is measured using an integrating method, which averages over time to get the current measurement and integrates over time to get a precise measurement value. a 5 to 600 milli-ohm sense resistor is connected to rshp and rshn as shown in the example schematic. the maximum input voltage at either rshp or rshn is +/-150 mv. the sense resistor should be properly sized to accommodate the lowest and highest expected charge and discharge currents, including suspend and/or standby currents. circuit traces from the sense resistor should be as short as practical without significant crossovers or feedthroughs. failure to use a single ground reference point at the negative side of the sense resistor can significantly degrade current measurement accuracy. the eeprom value, nullcurr , represents the zero zone current of the battery. this is provided as a calibration guardband for reading zero current. cur- rents below the +/- nullcurr (in ma) limit are read as zero and are not included in the capacity algorithm calculations. a typical value for nullcurr is 3 ma, so currents between -3 ma and +3 ma will be reported as zero and not included in the capacity calculations. the equation for current measurement resolution and sense resistor selection is shown in the following equation. equation 2-1: in-circuit calibration of the current is done using the smbus interface at time of manufacture to obtain absolute accuracy. the current measurement equation is: equation 2-2: cocurr is the ?correction offset for current? which compensates for any offset error in current measurement stored in eeprom. cfcurr is the ?correction factor for current? which compensates for any variances in the actual sense resistance over varying currents stored in eeprom. figure 2-1 shows the relationship of the cocurr and cfcurr values. figure 2-1: cocurr and cfcurr value relationship 2.3 auto-offset compensation accuracy drift is prevented using an automatic auto- zero self-calibration method, which ?re-zeroes? the current measurement circuit every aomint * 0.5 sec- onds when enabled. this feature can correct for drift in temperature during operation. the auto-offset compen- sation circuit works internally by disconnecting the rshp and rshn inputs and internally shorting these inputs to measure the zero input offset. the eeprom and calibration value cod is the true zero offset value of the particular module. 9.15 mv/r sense (milli-ohms) = current lsb (minimum current measurement if > nullcurr ) current lsb x 16384 = maximum current measurement possible i(ma) = (i_a/d ? cocurr ? cod ) * cfcurr /16384 where: i_a/d is the internal measurement ideal a/d response actual a/d response cfcurr cocurr actual current raw measurement
ps501 ds21818b-page 6 ? 2004 microchip technology inc. 2.4 voltage measurements the a/d input channels for cell and pack voltage mea- surements are the vc(1) to vc(4) pins. measurements are taken each measurement period when the a/d is active. the maximum voltage at any v cell x input pin is 19v absolute, but voltages above 18v are not sug- gested. the individual cell voltages are measured with an integration method to reduce any sudden spikes or fluctuations. the a/d uses an 11-bit resolution mode for these measurements. cell voltage inputs are read every measurement period, which is approximately every 500 milliseconds. this could be further extended by the use of sample mode, where a/d measurements are not activated every measurement period, depending on the configu- ration of samplelimit and nsample values. (see section 3.0 ?operational modes? for additional information.) for li ion, li-based, or even lead-acid applications, up to four (4) series cell voltages may be monitored individually. the highest voltage cell of the stack must be connected to vc(1). for some applications, the actual cell stack arrange- ment can be altered accordingly. the ps501 voltage input pins (v cell x pins) are capable of measuring up to 18v each. therefore, cell arrangements can be com- bined and the corresponding cell voltage thresholds can be adjusted. for example, a 2-cell li ion pack could actually be connected as a single 7.2v cell instead of two 3.6v cells. the values for the cell voltages would all be doubled, for example v cell 1 would equal the sum of two cells and only the vc(1) input pin would be used. each v cell x input circuit contains an internal resistive divider to reduce the external voltage input to a range that the internal a/d circuit can accommodate (150 mv maximum). these dividers are set based on a maximum cell voltage of 4.5 volts. a range of 340 mv with dividers, based on a maximum voltage of 20 volts, is used for pack voltage. the impedance at each v cell x input is roughly 100 kohms, but is only connected to ground (via the v ssa pins) when the actual voltage measurement is occurring. this corresponds to an insignificant amount of capacity drained through this circuit during the brief voltage measurement period, typically 45 ms every 500 ms. 2.4.1 impedance compensation since accurate measurement of pack voltage and cell voltages are critical to performance, the voltage measurements can be compensated for any imped- ance in the power path that might affect the voltage measurements. the eeprom value packresistance is used to compensate for additional resistance that should be removed. the equation for the compensation value (in ohms) is: equation 2-3: this requires modification of overall voltage sbdata function to compensate for pack resistance and shunt resistance of the current sense resistor. thus, the previous voltage equation is modified to: equation 2-4: the voltage measurement equation is: equation 2-5: covpack is the ?correction offset for pack voltage? which compensates for any offset error in voltage mea- surement (since the offset of the a/d is less than the voltage measurement resolution of +/- 16.5 mv, the covpack value is typically zero). cfvpack is the ?correction factor for pack voltage? which compensates for any variance in the actual a/d response versus an ideal a/d response over varying voltage inputs. the covpack and cfvpack are calibration constants that are stored in eeprom. v cell 1 and v cell 4 can also be compensated for impedance in the lines connecting to the ps501. vc1res is the resistance between the ps501 and the highest series cell. vc4res is the resistance between the ps501 and the lowest cell. this allows the ps501 to subtract any voltage drop due to current between the cell and the ps501. packresistance = trace resistance * 65535 (this is a 2-byte value so the largest value is 1ohm.) sbdata voltage value = vc(1) + measured current (ma) * packresistance /65535 v (mv) = (v_a/d ? covpack ) x cfvpack /2048 where: v_a/d is the internal measurement output
? 2004 microchip technology inc. ds21818b-page 7 ps501 figure 2-2 shows the relationship of the covpack and cfvpack values. figure 2-2: covpack and cfvpack value relationship in-circuit calibration of the voltage is done at the time of manufacture to obtain absolute accuracy in addition to high resolution. individual cell voltage measurements can be accurate to within 20 mv. the individual cell voltage inputs are also calibrated the same way the pack voltage is. there is one offset value, covcell , for all individual cells and up to four different correction factors, cfvcell1 through cfvcell4 , one for each cell input. 2.5 temperature measurements the a/d receives input from the internal temperature sensor to measure the temperature. optionally, an external thermistor can be connected to the v ntc pin which is also monitored by the a/d converter. an output reference voltage for use with an external thermistor is provided on the v reft pin. the a/d uses an 11-bit resolution mode for the temperature measurements. a standard 10 kohms at 25c negative-temperature- coefficient (ntc) device of the 103etb type is suggested for the optional external thermistor. one leg of the ntc should be connected to the v reft pin and the other to both the v ntc pin and a 3.65 kohms resis- tor to analog ground (v ssa ). the resistor forms the lower leg of a voltage divider circuit. to maintain high accuracy in temperature measurements, a 1% resistor should be used. a look-up table is used to convert the voltage measure- ment seen at the v ntc pin to a temperature value. the external thermistor should be placed as close as possi- ble to the battery cells and should be isolated from any other sources of heat that may affect its operation. calibration of the temperature measurements involves a correction factor and an offset exactly like the current and voltage measurements. the internal temperature measurement makes use of correction factor cftempi and offset cotempi , while the v ntc and v reft pins for the optional external thermistor make use of correction factor cftempe and offset cotempe . ideal a/d response actual a/d response cfvpack covpack raw measurement actual voltage
ps501 ds21818b-page 8 ? 2004 microchip technology inc. 3.0 operational modes the ps501 operates on a continuous cycle. the frequency of the cycles depends on the power mode selected. there are four power modes: run, sample, sleep and shelf-sleep. each mode has specific entry and exit conditions as listed below. 3.1 run mode whether the ps501 is in run mode or sample mode depends on the magnitude of the current. the run and sample mode entry-exit threshold is calculated using the eeprom parameter, samplelimit . samplelimit is a programmable eeprom value and cfcurr is an eeprom value set by calibration. entry to run mode occurs when the current is more than +/- samplelimit ma for two consecutive mea- surements. run mode may only be exited to sample mode, not to sleep mode, when sample mode is enabled. exit from run mode to sample mode occurs when the converted measured current is less than the +/- samplelimit ma threshold for two consecutive measurements. run mode is the highest power consuming mode. during run mode, all measurements and calculations occur once per measurement period. current, voltage and temperature measurements are each typically made sequentially during every measurement period. 3.2 sample mode entry to sample mode occurs when the measured current is less than +/- samplelimit (ee parameter) two consecutive measurements. sample mode may be exited to either run mode or sleep mode. while in sample mode, measurements of voltage, cur- rent and temperature occur only once per nsample counts of measurement periods, where nsample is a programmable eeprom value. calculations of state- of-charge, smbus requests, etc. still continue at the normal run mode rate, but measurements only occur once every measurement period x nsample . the minimum value for nsample is two. the purpose of sample mode is to reduce power con- sumption during periods of inactivity (low rate charge or discharge). since the analog-to-digital converter is not active, except every nsample counts of measurement periods, the overall power consumption is significantly reduced. example 3-1: configuration 3.3 low-voltage sleep mode entry to sleep mode can only occur when the measured pack voltage at the vc(1) input is below a preset limit, set by the eeprom value sleepvpack (in mv). sleep mode may be exited to run mode, but only when one of the wake-up conditions is satisfied. while in sleep mode, no measurements occur and no calculations are made. the fuel gauge display is not operational, no smbus communications are recog- nized and only a wake-up condition will permit an exit from sleep mode. sleep mode is one of the lowest power consuming modes and is used to conserve battery energy following a complete discharge. there are two levels of low-voltage sleep mode that can be used, each with a different wake-up criteria. default low-power mode will use 25 a typical and will wake-up when the voltage exceeds the wakeup voltage level. by setting bit 1 of the wakeup register to ? 1 ?, the ultra low-power mode can be used. this will be entered by low voltage, but wake-up occurs by pulling the smbus lines high. ultra low-power mode uses less than 1 a. 3.4 shelf-sleep mode shelf-sleep mode is used to put the ps501 into low- power mode, regardless of voltage level, for long term storage of battery packs. it is entered by an smbus command. it is exited by the conditions selected in the wakeup register. these can be voltage, current, gpio or smbus activity. if any of these four are selected for wake-up, the shelf-sleep mode will be low-power mode and will draw 25 a typical. if none of these options are selected and bit 3 of the wakeup register is set, the shelf-sleep mode will be ultra low-power mode, which will draw less than 1 a and wake-up will be by pulling smbus high. measurement period is 500 ms samplelimit is set to 20 nsample is set to 16 result: run/sample mode entry-exit threshold = 20 ma during sample mode, measurements will occur every: 16 measurement periods of 500 ms = every 8 seconds
? 2004 microchip technology inc. ds21818b-page 9 ps501 table 3-1: wakeup eeprom value table 3-2: wakelevels eeprom value table 3-3: power mode summary bit name function 7 wakeio wake-up from i/o activity 6 wakebus wake-up from smbus activity 5 wakecurr wake-up from current 4 wakevolt wake-up from voltage 3 enable shelf-sleep use ultra low-power mode for shelf-sleep mode. all other bits must be zero. 1 lv sleep mode use ultra low-power mode as low-voltage sleep mode 0 zero remcap set remap to zero when entering low-voltage sleep mode wakeup voltage (2:0) voltage purpose 000 6.4v 2 cells li ion 001 6.66v 2 cells li ion 010 8.88v 2 cells li ion 011 9.6v 3 cells li ion 100 9.99v 3 cells li ion 101 11.1v 3 cells li ion 110 12.8v 4 cells li ion 111 13.3v 4 cells li ion wakeup current (7:3) voltage purpose 00000 minimum v across sense resistor 11000 typical recommended v across sense resistor 11111 maximum v across sense resistor mode entry exit notes run measured current > preset threshold (set by samplelimit ) measured current < preset threshold (set by samplelimit ) highest power consumption and accuracy for rapidly changing current. sample measured current < preset threshold (set by samplelimit ) measured current > preset threshold (set by samplelimit ) saves power for low, steady current consumption. not as many measurements needed. measurements made every nsample periods. sleep v pack < sleepvpack and in sample mode wakeup voltage level exceeded (low-power mode) or smbus pulled high (ultra low-power mode) no measurements made. shelf-sleep smbus command wakeup register conditions met (low-power mode) or smbus pins pulled high (ultra low-power mode) no measurements made.
ps501 ds21818b-page 10 ? 2004 microchip technology inc. 4.0 capacity monitoring the ps501 internal cpu uses the voltage, current and temperature data from the a/d converter, along with parameters and cell models, to determine the state of the battery and to process the sbdata function instruction set. by integrating measured current, monitoring voltages and temperature, adjusting for self-discharge and checking for end-of-charge and end-of-discharge conditions, the ps501 creates an accurate fuel gauge under all battery conditions. 4.1 capacity calculations the ps501 calculates state-of-charge and fuel gaug- ing functions using a ?coulomb counting? method, with additional inputs from battery voltage and temperature measurements. by continuously and accurately mea- suring all the current into and out of the battery cells, along with accurate three-dimensional cell models, the ps501 is able to provide accurate predictions of soc and run-time. the capacity calculations consider two separate states: charge acceptance or capacity increasing (ci) and dis- charge or capacity decreasing (cd). the ci state only occurs when a charge current larger than the eeprom nullcurr value is measured. otherwise, while at rest and/or while being discharged, the state is cd. conditions must persist for at least nchangestate measurement periods for a valid state change between cd and ci. a minimum value of 2 is suggested for nchangestate . regardless of the ci or cd state, self-discharge is also calculated and subtracted from the integrated capacity values. even when charging, there is still a self-discharge occurring in the battery. to compensate for known system errors in the capacity calculations, a separate error term is also continuously calculated. this term is the basis for the sbdata value of maxerror. two error values are located in eeprom. the currerror value is the inherent error in current measurements and should be set based on the selec- tion of a sense resistor and calibration results. the selfdischrgerr value is the error in the parameter tables for self-discharge and depends on the accuracy of the cell chemistry model for self-discharge. since the ps501 electronics also drain current from the battery system, another eeprom value allows even this minor drain to be included in the capacity calcula- tions. the pwrconsumption value represents the drain of the ic and associated circuitry, including additional safety monitoring electronics if present. a typical value of 77 represents the module?s nominal power consumption, including the ps501 typical consumption. the total capacity added or subtracted from the battery (change in charge) per measurement period is expressed by the following formula: equation 4-1: the error terms are always subtracted, even though they are +/- errors, so that the fuel gauge value will never be overestimated. current draw of the ps501 and the self-discharge terms are also always subtracted. the sbdata value, maxerror , is the total accumulated error as the gas gauge is running. the battery current will be precisely measured and integrated in order to calculate total charge removed from or added to the battery. based on look-up table values, the capacity is adjusted for self-discharge relative to current, temperature and soc. 4.2 discharge termination discharge termination is determined based on the end-of-discharge (eod) voltage point. the voltage level at which this point occurs can be chosen to be constant, or to change depending on the temperature and discharge rate, since these factors affect the volt- age curve and total capacity of the battery. the eod voltage parameter table predicts the voltage point at which this eod will be reached, based on discharge rate and temperature. the ps501 will monitor temperature and discharge rate continuously and update the veodx in real-time. when the voltage measured on the cell is below eod voltage for the duration of eodrecheck x periods (500 ms), a valid eod has occurred. when a valid eod has been reached, the terminate_discharge_alarm bit (bit 11) in batterystatus will be set. this will cause an alarmwarning condition with this bit set. additionally, the remaining_time_alarm and/or remaining_capacity_alarm bits can be set first to give a user defined early warning prior to the terminate_discharge_alarm. the remaining time alarm will trigger in battery status when the remain- ing time calculation falls below a threshold set by the smbus command. the remaining capacity alarm will be set in battery status when the capacity falls below a threshold set by the smbus command. use an smbus write command to remaining timealarm (command code 0x02) or remainingcapacityalarm (command code 0x01) to set these values. ? charge = i ? t (the current integrated over time) - currerror (current measurement error) - pwrconsumption * ? t (ps501 i dd ) - % of self-discharge * fcc - selfdischrgerr (self-discharge error)
? 2004 microchip technology inc. ds21818b-page 11 ps501 4.3 capacity relearn at discharge termination to maintain accurate capacity prediction ability, the fullcapacity value is relearned on each discharge, which has reached a valid eod after a previous valid fully charged condition (eoc). if a partial charge occurs before reaching a valid eod, then no relearn will occur. if the discharge rate at eod is greater than the ?c-rate? adjusted value in relearncurrlim, then no relearn will occur. when a valid eod has been reached, then the error cal- culations represented by the sbdata value of maxerror will be cleared to zero. if appropriate, the relearned value of fullcapacity (and fullchargecapacity ) will also be updated at this time. 4.4 discharge termination voltage look-up table 4.4.1 near empty shutdown point as the graph in table 4-1 shows, available capacity in the battery varies with temperature and discharge rate. since the remaining capacity will vary with temperature and discharge rate, a near empty shutdown point will also vary with temperature and discharge rate. knowing the discharge rate that occurs in the system during the shutdown process and knowing the tempera- ture can pinpoint the exact save to disk point that will always leave the perfect shutdown capacity. the ps501 uses this information to tailor the gas gauge to the sys- tem and the remaining capacity and rsoc fuel gauge function will always go to zero at the efficient shutdown point. the table will use the voltage points at which this happens as the error correction and fullcapacity relearn point. this will ensure a relearn point before shutdown occurs and will correct any error in remaining capacity, also to ensure proper shutdown reserve energy. the shutdown point has to equal the capacity required to shut down the system under the conditions of the shutdown. that is, looking at the curve that represents the actual discharge c-rate that occurs during the sys- tem shutdown function, we must stop discharge and initiate shutdown when the system has used capacity equal to that point on the shutdown c-rate curve. this is because no matter what the c-rate is when the shut- down point is reached, the system will automatically switch to the c-rate curve that represents the actual current draw of the shutdown function. so it doesn't matter if the system is in high discharge or low dis- charge, it will be in ?shutdown? discharge conditions when shutdown begins and there must be enough capacity left. an example is a computer?s save to disk function. table 4-1 shows that the system will always shutdown at the same capacity point regardless of c-rate condi- tions (since the c-rate of the save to disk procedure is a constant). thus, we can automatically have an rsoc that is compensated for c-rate; it will go to zero when the capacity used is equal to the point at which shutdown occurs. ignoring the effects of temperature, we could mark the capacity used up to the shutdown point of the shutdown curve. all the shutdown voltage would then represent the same capacity and rsoc would always become zero at this capacity and fcc would always equal this capacity, plus the residual capacity of the save to disk curve. to compensate for temperature, we can look at the series of curves that represent the shutdown c-rate at different temperatures. the ps501 implementation is to measure the temperature and choose a scaled rsoc value that will go to zero at the save to disk point at this temperature, assuming the temperature does not change. if it does change, then an adjustment to rsoc will be needed to make it go to zero at the shutdown point. taking temperature into consideration, the amount of capacity that can be used before shutdown is a constant as c-rate changes, but not constant as tem- perature changes. thus, in the look-up table (lut), the individual temperature columns will have voltage points that all represent the same capacity used, but the rows across temperature points (c-rate rows) will represent the different capacity used. to compensate rsoc and rm, interpolation will be used and the compensation adjustment will happen in real-time to avoid sudden drops or jumps. every time the temperature decreases by one degree, a new inter- polated value will be subtracted from rsoc and rm. every time the temperature increases by one degree, rsoc and rm will be held constant until discharged capacity equals the interpolated value that should have been added to rsoc and rm (to avoid capacity increases during discharge). with this interpolation happening in real-time, there will be no big jumps or extended flat periods as we cross over boundaries in the lut. this compensation will not begin until after the fully charged status is reset, allowing rsoc to be 100% always when the battery is full. 4.5 age compensation the voltage eod points will be compensated due to the age of the cells. a linear factor, agefactor , will be applied to the voltage points as a function of cyclecount . the voltage levels will decrease as the battery pack ages to model the flattening of the voltage vs. capacity curve that naturally happens to battery cells.
ps501 ds21818b-page 12 ? 2004 microchip technology inc. table 4-1: v_eod look-up table the above table is an example of the various voltage values that will signal the shutdown points as a function of temperature and discharge rate. also shown is the amount of capacity left after shutdown that will compensate rsoc. table 4-2 shows the actual names of the values in the eeprom. table 4-2: value names in the eeprom table 4-3: value definitions in the eeprom < -10 < 0 < 10 < 20 < 30 < 40 < 50 > 50 < 0.2c v1 v2 v3 ? < 0.5c < 0.8c < 1.1c < 1.4c < 1.7c < 2.0c > 2.0c ? v62 v63 v64 capacity 20% 10% 5% 3% 0% 0% 0% 0% teod(1) teod(2) teod(3) teod(4) teod(5) teod(6) teod(7) teod(8) ceod(1) veod1(1) veod1(2) veod1(3) veod1 (4) veod1(5) veod1(6) veod1(7) veod1(8) ceod(2) veod2(1) veod2(2) veod2(3) veod2 (4) veod2(5) veod2(6) veod2(7) veod2(8) ceod(3) veod3(1) veod3(2) veod3(3) veod3 (4) veod3(5) veod3(6) veod3(7) veod3(8) ceod(4) veod4(1) veod4(2) veod4(3) veod4 (4) veod4(5) veod4(6) veod4(7) veod4(8) ceod(5) veod5(1) veod5(2) veod5(3) veod5 (4) veod5(5) veod5(6) veod5(7) veod5(8) ceod(6) veod6(1) veod6(2) veod6(3) veod6 (4) veod6(5) veod6(6) veod6(7) veod6(8) ceod(7) veod7(1) veod7(2) veod7(3) veod7 (4) veod7(5) veod7(6) veod7(7) veod7(8) ceod(8) veod8(1) veod8(2) veod8(3) veod8 (4) veod8(5) veod8(6) veod8(7) veod8(8) fccp(1) fccp(2) fccp(3) fccp(4) fccp(5) fccp(6) fccp(7) fccp(8) teod 8 coded bytes typ: 5, 20, 35, 50, 80, 113, 150, 150 range: 1-255 per byte eod temperature boundaries, 8 increasing values of te mperature coded as teodx = (tcelsius * 10 + 200)/4 ceod 8 coded bytes typ: 19, 32, 48, 64, 77, 90, 109,1 09 range: 1-255 eoc c-rate boundaries, 8 increasing values of c-rates coded: ceodx = c-rate * (256/28/r f ), where r f is the rate factor (r factor ) otp eprom parameter. for r f = 7, ceodx = c-rate * 64. thus, a value of 32 is one-half c, etc. fccp coded % typ: 50, 25, 12, 8, 0, 0, 0 range: 1-255 unusable residual capacity before save to disk, corresponding to temperature, 255 = 100% veod coded typ: 75 range: 1-255 end-of-discharge voltage, voltage = 2700 + 4 * veod. cell voltage at which save to disk is signaled.
? 2004 microchip technology inc. ds21818b-page 13 ps501 5.0 charge control a sbs configuration normally allows the smart battery to broadcast the chargingvoltage and chargingcurrent values to the smart battery charger (smbus address 12 hex) to ?control? when to start charge, stop charge and when to signal a valid ?fully charged? condition. a larmwarnings are also sent from the smart battery (smbus address 16 hex) to the smart battery charger. alternately, the smbus host or a ?level 3? smart battery charger may simply read the sbdata values for chargingvoltage and chargingcurrent from the smart battery directly. the host or ?level 3? smart battery charger is also required to read the sbdata value of batterystatus to obtain the appropriate alarm and status bit flags. when used in this configuration, the chargingcurrent and chargingvoltage broadcasts can be disabled from the smart battery by setting the charger_mode (bit 14) in the batterymode regis- ter. the ps501 ics support all of these functions. (please refer to the sbs smart battery charger specification for a definition of the ?level 3? smart battery charger.) the chargingcurrent and chargingvoltage registers contain the maximum charging parameters desired by the particular chemistry, configuration and environmen- tal conditions. the environmental conditions include the measured temperature and the measured cell or pack voltages. for li-based systems, chargingvoltage should be set to the product of the eocvolt and cells values from the eeprom: equation 5-1: the chargingcurrent value is set to a maximum using the chrgcurr value from the eeprom. for lithium systems, both chargingcurrent and chargingvoltage values are maximums. when the current reaches chrgcurr , it will be held constant at this value. then, when the voltage reaches chrgvolt , the current must be reduced so that the voltage will be constant and not exceed the maximum. this is accomplished by setting chargingcurrent to chrgcurroff . for safety reasons, this current change also occurs when the temperature limits are exceeded. when temperature or voltage lim- its are exceeded, the value of chargingcurrent changes to the chrgcurroff value from the eeprom. when a valid end-of-charge (eoc) condition is detected and a fully charged state is reached, the chargingcurrent value is set equal to the chrgcurroff value. when chargingcurrent is set to the chrgcurroff value, no broadcasts of either chargingcurrent or charging- voltage will occur unless a charge current greater than nullcurr is detected by the a/d measurements. temperature limits are set using the chrgmaxtemp , dischrgmaxtemp and chrgmintemp values from eeprom. these values represent the temperature limits within which chargingcurrent will be set to chrgcurr . temperatures outside these limits will cause chargingcurrent to be set to chrgcurroff. if chargingcurrent is set to chrgcurroff and the mea- sured temperature is greater than dischrgmaxtemp and less than chrgmaxtemp and a charge current is measured which is significantly larger than the chrgcurroff value, then chargingcurrent will be set to chrgcurr unless a fully charged condition has already been reached. if the charger_mode bit in the batterymode regis- ter is cleared (enabling broadcasts of chargingcurrent and chargingvoltage ), then these broadcasts will occur every nchrgbroadcast measurement cycle. the smart battery data and smart battery charger specifications require that chargingcurrent and chargingvoltage broadcasts occur no faster than once per 5 seconds and no slower than once per 60 seconds when charging is occurring or desired. this requires that the nchrgbroadcast value must be set between 10 and 120. the smbus specification also requires that no broadcasts occur during the first 10 seconds after smbus initialization. example 5-1: configuration chargingvoltage = eocvolt x cells measurement cycle is 500 msec nchrgbroadcast = 100 decimal chrgcurr = 2500 decimal chrgcurroff =10 decimal chrgmaxtemp = 162 decimal dischrgmaxtemp = 137 decimal chrgmintemp =50 decimal results: chargingcurrent and chargingvoltage broadcasts: 100 cycles of 500 msec = every 50 seconds broadcast delay after smbus initialization: 10 seconds chargingcurrent if temperature > 45c: 10 ma chargingcurrent if temperature < 0c: 10 ma chargingcurrent if temperature < 35c and > 0c: 2500 ma
ps501 ds21818b-page 14 ? 2004 microchip technology inc. 5.1 full charge detection methods for a typical lithium ion constant-current/constant- voltage charge system, the ps501 will monitor the taper current that enters the battery once the battery has reached the final voltage level of the charger. once the taper current falls to a certain level, indicating that the battery is full, the end-of-charge (eoc) will be trig- gered. different taper currents will be used for different temperatures. see the parameter explanation in section 9.0 ?parameter setup? for details. when a valid fully charged eoc condition is detected, the following actions occur: the fully_charged status bit (bit 5) in the sbdata value of batterystatus is set to ? 1 ? to indicate a full condition. (this will remain set until relativestateofcharge drops below the clrfullychrg value in eeprom.) relativestateofcharge is set to 100%. chargingcurrent is set to chrgcurroff value. sbdata value for maxerror is cleared to zero percent (0%). the terminate_charge_alarm bit (bit 14) is set in batterystatus and an alarmwarning broadcast is sent to the smbus host and smart battery charger addresses. the overchrg value is incremented for any charge received above 100% after a valid fully charged eoc condition. control flags for internal operations are set to indicate a valid full charge condition was achieved. other batterystatus or alarmwarning flag bits may also be set depending on the conditions causing the eoc. - the charge timer, eoctimer, is exceeded - cell voltage is higher than tcavolt 5.2 temperature algorithms the ps501 smbus smart battery ic provides multiple temperature alarm set points and charging conditions. the following eeprom parameters control how the temperature alarms and charging conditions operate. hightempal: when the measured temperature is greater than hightempal , the over_temp_alarm is set. if the battery is charging, then the terminate_charge_alarm is also set. chrgmintemp, dischrgmaxtemp and chrgmaxtemp: if the measured temperature is less than chrgmintemp , the chargingcurrent is set to chrgcurroff and the chargingvoltage is set to chrgvolt to communicate to the charger that the non-c harging state of current and voltage should be given. when measured temperature is greater than chrgmaxtemp and the system is charg- ing, or greater than dischrgmaxtemp and the system is discharging, then chargingcurrent is set to chrgcurroff and the chargingvoltage is set to chrgvoltoff also. otherwise, chargingcurrent = chrgcurr and chargingvoltage = chrgvolt . 6.0 cell balancing the ps501 has internal cell balancing loads with which to draw extra current away from higher voltage cells. there are internal 500 ohm resistors, which will draw up to 8.4 ma of current from each cell, depending on the cell voltage. the cell balancing algorithm will moni- tor individual cell voltages and the difference between them. when the difference between any cells exceeds the eeprom parameter, vcelldiffmax , the resistor load will be applied to the higher cell until it is within vcelldiffresetmax of the lowest. cell balancing will only be applied during the charging state to maintain run time during discharge. determination of cell balance requirement will be made near end-of-charge, when the capacity difference results in a cell voltage difference. once this determina- tion is made, cell balancing will commence on the charge cycle and remain in effect for the entire charge cycle. upon discharging, cell balancing will be disabled to preserve run time. once the near empty point is reached again, determination will be made as to whether correct hysteresis has been reached to disable the cell balancing for the next charge cycle.
? 2004 microchip technology inc. ds21818b-page 15 ps501 figure 6-1: cell balancing cell balancing: entry from main charging ? set appropriate cell balancing (adcon1) per active balance flags (1 to 3) set flag_cell_balance_on = 1 yes no set appropriate cell balance flag(s) to balance during charge (3 maximum) set all cell balance flags off set flag_cell_balance_on = 0 soc < r_e_imbalance_soc (%) ? any v cell delta > r_e_vcell_imbalance_set ? yes yes no any v cell balance flags set ? this algorithm makes the imbalance determination on the discharge cycle near eod and uses the entire charge cycle for balancing (good for low balance currents) exit back to main yes no no flag_cell_imbalance_on set ? any v cell delta > r_e_vcell_imbalance_reset ? yes no force adcon1 cb bits to 0 (no balancing during discharge) no yes
ps501 ds21818b-page 16 ? 2004 microchip technology inc. 7.0 gpio configuration gpios can be set up to act as inputs or outputs that are based on conditions involving sbdata parameters or gpio levels compared to constants. this powerful pro- gramming model allows for customizing gpio to set on any possible fuel gauge conditions and reset on any other possible fuel gauge conditions in any groupings. table 7-1: gpio configurations gpios configured above as standard logic output can be programmed to activate or reset in response to any group of fuel gauge conditions. each ?condition? is defined by 4 bytes. table 7-2: gpio conditions name length definition gpiostate 2 initialized default state (positive logic) gpiodirection 2 initialized direction: 1 = input 0 = output gpioconfig 2 gpio configuration bit 8: 1 = pull-ups/downs disabled 0 = pull-downs enabled bits 7:0: if input: 1 = pulled down 0 = pulled up if output: 1 = led drive (gpio0-7 only) 0 = standard logic gpiopolarity 2 ?polarity? mask applied to invert positive logic byte condition definition byte 1 flags bit 7: 1 signifies last condition in group bit 4: combination function (1:and, 0:or) bit 3: signed (1) or unsigned (0) bits 2:0 comparison function (0 : >, 1 : <, 2 : =, 3 : and, 4 : nor) byte 2 condition selection x00-x3f ? sbdata command code x40 ? state flags x41 ? gpio flags x42 ? v cell -min x43 ? v cell -max x44 ? v cell -diff x45 ? misc. flags byte 3 byte 4 condition threshold constant
? 2004 microchip technology inc. ds21818b-page 17 ps501 each condition in the table is processed by applying a ?comparison function? to the selected data (?condition selection?) and the given constant (?condition thresh- old?). the result of this operation (?true? or ?false?) from each condition in the group is combined as dictated by the ?and-or? ?combination function? bit in the flag byte. because the ?and? function has precedence over the ?or?, processing the cg can be described as or?ing subgroups of ands (see example 7-1 below). one 8-bit timer (clocked at 500 msec) is associated with all 16 csf(s). the timer compared to its threshold is an implied ?and? term to the cg (i.e., if processing of the cg to set the csf results in ?true?, the timer is incremented and if timer >= threshold, the sf is set; otherwise, the sf is not set even though the gc is sat- isfied). if processing of the cg to set the csf results in ?false?, the timer is set to zero. the timer is not allowed to increment past the threshold. the conditions in the order they are stored in memory will build the activation equation until bit 7 of byte 1 is set, signifying the last condition of the group. at that point, the next group of conditions is the reset equation. when the next to last condition bit is set, a new activation group begins. example 7-1: condition groups table 7-3: conditions for example 7-1 example condition group: (v cell -min < 3200) .and. (curr > 100) .or. (temp > 60) .and. (curr > 200) because of precedence the equation would be interpreted: ((v cell -min < 3200) .and. (curr > 100)) .or. ((temp > 60) .and. (curr > 200)) example reset condition group: (v cell -min > 3200) or (curr = 200) condition byte 1 byte 2 byte 3, 4 description 1 x01 x42 x0c80 or v cell -min < 3200 2 x10 x0a x0064 and curr > 100 3 x00 x08 x0d02 or temp > 60c (3330 degrees k * 10) 4 x80 x0a x00c8 and curr > 200 (last condition bit set) 1 x00 x42 x0c80 or v cell -min > 3200 2 x82 x0a x00c8 or curr = 200 (last condition bit set) table 7-4: parameters name length description safe_gpio_mask_00 2 mask applied to the csf, if <> 0 , gpio is set safe_gpio_mask_01 2 mask applied to the csf, if <> 0 , gpio is set safe_gpio_mask_02 2 mask applied to the csf, if <> 0 , gpio is set safe_gpio_mask_03 2 mask applied to the csf, if <> 0 , gpio is set safe_gpio_mask_04 2 mask applied to the csf, if <> 0 , gpio is set safe_gpio_mask_05 2 mask applied to the csf, if <> 0 , gpio is set safe_gpio_mask_06 2 mask applied to the csf, if <> 0 , gpio is set safe_gpio_mask_07 2 mask applied to the csf, if <> 0 , gpio is set safe_gpio_mask_08 2 mask applied to the csf, if <> 0 , gpio is set safe_gpio_mask_09 2 mask applied to the csf, if <> 0 , gpio is set safe_gpio_mask_10 2 mask applied to the csf, if <> 0 , gpio is set safe_gpio_mask_11 2 mask applied to the csf, if <> 0 , gpio is set safe_timer_limit_0 1 timer threshold/limit (500 msec tics) safe_timer_limit_1 1
ps501 ds21818b-page 18 ? 2004 microchip technology inc. 7.1 led parameters when configured as led drivers, the following parameters determine the state-of-charge at which each led will turn on. table 7-5: led parameters safe_timer_limit_2 1 safe_timer_limit_3 1 safe_timer_limit_4 1 safe_timer_limit_5 1 safe_timer_limit_6 1 safe_timer_limit_7 1 safe_timer_limit_8 1 safe_timer_limit_9 1 safe_timer_limit_10 1 safe_timer_limit_11 1 safe_timer_limit_12 1 safe_timer_limit_13 1 safe_timer_limit_14 1 safe_timer_limit_15 1 safe_flag_count 1 number of csf(s) to process, 0-16 (there must be 2 condition groups (cgs) per csf) safe_condition 4 condition (start of table) . . . 4 condition safe_condition 4 condition (end of table) table 7-4: parameters (continued) name length description name length definition led_mask 1 mask defining gpio(s) used for led display(s) ( 1 = led) led_value_0 1 gpio 0 soc value (soc >= led_value, led = on) led_value_1 1 gpio 1 soc value (soc >= led_value, led = on) led_value_2 1 gpio 2 soc value (soc >= led_value, led = on) led_value_3 1 gpio 3 soc value (soc >= led_value, led = on) led_value_4 1 gpio 4 soc value (soc >= led_value, led = on) led_value_5 1 gpio 5 soc value (soc >= led_value, led = on) led_value_6 1 gpio 6 soc value (soc >= led_value, led = on) led_value_7 1 gpio 7 soc value (soc >= led_value, led = on) led_ichg 2 current threshold for led display led_dutycycle 1 duty cycle of led drivers gpio_switchmask 2 mask for switch input(s). if switch is active-high, all bits are ? 0 ? except switch pin. if switch is active-low, all bits are ? 1 ? except switch pin. led_display_time 1 number of 500 ms periods leds are lit after switch press
? 2004 microchip technology inc. ds21818b-page 19 ps501 8.0 smbus/sbdata interface the ps501 uses a two-pin system management bus (smbus) protocol to communicate to the host. one pin is the clock and one pin is the data. the smbus port responds to all commands in the smart battery data specification (sbdata). to receive information about the battery, the host sends the appropriate commands to the smbus port. certain alarms, warnings and charging information may be sent to the host by the ps501 automatically. the smbus protocol is explained in this chapter. the sbdata command set is summarized in table 8-1. the ps501 smbus communications port is fully com- pliant with the system management bus specification, version 1.1 and supports all previous and new requirements, including bus time-outs (both slave and master), multi-master arbitration and collision detec- tion/recovery. the smbus port serves as a slave for both read and write functions, as well as a master for write word functions. smbus slave protocols supported include read word, write word, read block and write block. master mode supports write word protocols. the ps501 meets and exceeds the smart battery data specification, version 1.1/1.1a requirements. the ps501 is compliant with system management bus specification 1.0. the ps501 fully implements the smart battery data (sbdata) specification v1.1. the sbdata specification defines the interface and data reporting mechanism for an sbs compliant smart battery. it defines a consistent set of battery data to be used by a power management system to improve battery life and system run-time, while providing the user with accurate information. this is accomplished by incorporating fixed, measured, calculated and predicted values, along with charging and alarm messages, with a simple communications mechanism between a host system, smart batteries and a smart charger. the ps501 provides full implementation of the sbdata set with complete execution of all the data functions, including sub-functions and control bits and flags, com- pliance to the accuracy and granularity associated with particular data values and proper smbus protocols and timing. 8.1 sbdata function description the following subsections document the detailed operation of all of the individual sbdata commands. 8.1.1 manufactureraccess (0x00) internal use only. 8.1.2 remainingcapacityalarm (0x01) sets or reads the low capacity alarm value. whenever the remaining capacity falls below the low capacity alarm value, the smart battery sends alarm warning messages to the smbus host with the remaining_capacity_alarm bit set. a low capacity alarm value of ? 0 ? disables this alarm. 8.1.3 remainingtimealarm (0x02) sets or reads the remaining time alarm value. whenever the averagetimetoempty falls below the remaining time value, the smart battery sends alarm warning messages to the smbus host with the remaining_time_alarm bit set. a remaining time value of ? 0 ? disables this alarm.
ps501 ds21818b-page 20 ? 2004 microchip technology inc. table 8-1: smart battery data functions sbdata function name command code access parameter reference units manufactureraccess ? write (1) 0x00 r/w manufactureraccess ? read (1) 0x00 r/w remainingcapacityalarm 0x01 r/w remcapal mah or 10 mwh remainingtimealarm 0x02 r/w remtimeal minutes batterymode 0x03 r/w bit code atrate 0x04 read mah or 10 mwh atratetimetofull 0x05 read minutes atratetimetoempty 0x06 read minutes atrateok 0x07 read binary 0 / 1 (lsb) temperature 0x08 read 0.1k voltage 0x09 read mv current 0x0a read ma averagecurrent 0x0b read ma maxerror 0x0c read % relativestateofcharge 0x0d read % absolutestateofcharge 0x0e read % remainingcapacity 0x0f read mah or 10 mwh fullchargecapacity 0x10 read mah or 10 mwh runtimetoempty 0x11 read minutes averagetimetoempty 0x12 read minutes averagetimetofull 0x13 read minutes chargingcurrent 0x14 read chrgcurr or chrgcurroff ma chargingvoltage 0x15 read chrgvolt or chrgvoltoff mv batterystatus 0x16 read batstatus bit code cyclecount 0x17 read cycles integer designcapacity 0x18 read designcapacity mah or 10 mwh designvoltage 0x19 read designvpack mv specificationinfo 0x1a read sbdataversion coded manufacturedate 0x1b read date coded serialnumber 0x1c read serialnumber not specified reserved ? ? ? ? manufacturername 0x20 read mfgname ascii text string devicename 0x21 read devicename ascii text string devicechemistry 0x22 read chemistry ascii text string manufacturerdata 0x23 read mfgdata hex string optionalmfgfunction4 0x3c read v1 cell voltage mv optionalmfgfunction3 0x3d read v2 cell voltage mv optionalmfgfunction2 0x3e read v3 cell voltage mv optionalmfgfunction1 0x3f read v4 cell voltage mv note 1: reserved.
? 2004 microchip technology inc. ds21818b-page 21 ps501 8.1.4 batterymode (0x03) this function selects the various battery operational modes and reports the battery?s capabilities, modes and condition. bit 0: internal_charge_controller bit set indicates that the battery pack contains its own internal charge controller. when the bit is set, this optional function is supported and the charge_controller_enabled bit will be activated. bit 1: primary_battery_support bit set indicates that the battery pack has the ability to act as either the primary or secondary battery in a sys- tem. when the bit is set, this optional function is supported and the primary_battery bit will be activated. bit 2-6: reserved bit 7: condition_flag bit set indicates that the battery is requesting a conditioning cycle. this typically will consist of a full charge to full discharge, back to full charge of the pack. the battery will clear this flag after it detects that a conditioning cycle has been completed. bit 8: charge_controller_enabled bit is set to enable the battery pack?s internal charge controller. when this bit is cleared, the internal charge controller is disabled (default). this bit is active only when the internal_charge_controller bit is set. bit 9: primary_battery bit is set to enable a battery to operate as the primary battery in a system. when this bit is cleared, the battery operates in a secondary role (default). this bit is active only when the primary_battery_support bit is set. bit 10-12: reserved bit 13: alarm_mode disables the smart battery?s transmission of the batterystatus bits on an alarm condition. will reset to enabled after 60 seconds. bit 14: charger_mode enables or disables the smart battery?s transmission of chargingcurrent and chargingvoltage messages to the smart battery charger. when set, the smart battery will not transmit chargingcurrent and chargingvoltage values to the charger. when cleared, the smart battery will transmit the chargingcurrent and chargingvoltage values to the charger when charging is desired. bit 15: capacity_mode indicates if capacity information will be reported in ma/ mah or 10 mw/10 mwh. when set, the capacity informa- tion will be reported in 10 mw/10 mwh. when cleared, the capacity information will be reported in ma/mah. 8.1.5 atrate (0x04) atrate is a value of current or power that is used by three other functions: atratetimetofull , atratetimetoempty and atrateok : atratetimetofull returns the predicted time to full charge at the atrate value of charge current. atratetimetoempty function returns the predicted operating time at the atrate value of discharge current. atrateok function returns a boolean value that predicts the battery?s ability to supply the atrate value of additional discharge current for 10 seconds. 8.1.6 atratetimetofull (0x05) returns the predicted remaining time to fully charge the battery at the atrate value (ma). the atratetimetofull function is part of a two-function call set used to deter- mine the predicted remaining charge time at the atrate value in ma. it will be used immediately after the smbus host sets the atrate value. 8.1.7 atratetimetoempty (0x06) returns the predicted remaining operating time if the battery is discharged at the atrate value. the atratetimetoempty function is part of a two-function call set used to determine the remaining operating time at the atrate value. it will be used immediately after the smbus host sets the atrate value. 8.1.8 atrateok (0x07) returns a boolean value that indicates whether or not the battery can deliver the atrate value of additional energy for 10 seconds (boolean). if the atrate value is zero or positive, the atrateok function will always return true. the atrateok function is part of a two- function call set used by power management systems to determine if the battery can safely supply enough energy for an additional load. it will be used immediately after the smbus host sets the atrate value. 8.1.9 temperature (0x08) returns the cell pack?s internal temperature in units of 0.1k. 8.1.10 voltage (0x09) returns the pack voltage (mv). 8.1.11 current (0x0a) returns the current being supplied (or accepted) through the battery?s terminals (ma).
ps501 ds21818b-page 22 ? 2004 microchip technology inc. 8.1.12 averagecurrent (0x0b) returns a one-minute rolling average based on at least 60 samples of the current being supplied (or accepted) through the battery?s terminals (ma). 8.1.13 maxerror (0x0c) returns the expected margin of error (%) in the state- of-charge calculation. for example, when maxerror returns 10% and relativestateofcharge returns 50%, the relativestateofcharge is actually between 50% and 60%. the maxerror of a battery is expected to increase until the smart battery identifies a condition that will give it higher confidence in its own accuracy. for example, when a smart battery senses that it has been fully charged from a fully discharged state, it may use that information to reset or partially reset maxerror . the smart battery can signal when maxerror has become too high by setting the condition_flag bit in batterymode . 8.1.14 relativestateofcharge (0x0d) returns the predicted remaining battery capacity expressed as a percentage of fullchargecapacity (%). 8.1.15 absolutestateofcharge (0x0e) returns the predicted remaining battery capacity expressed as a percentage of designcapacity (%). note that absolutestateofcharge can return values greater than 100%. 8.1.16 remainingcapacity (0x0f) returns the predicted remaining battery capacity. the remainingcapacity value is expressed in either current (mah) or power (10 mwh), depending on the setting of the batterymode ?s capacity_mode bit. 8.1.17 fullchargecapacity (0x10) returns the predicted pack capacity when it is fully charged. it is based on either current or power, depending on the setting of the batterymode ?s capacity_mode bit. 8.1.18 runtimetoempty (0x11) returns the predicted remaining battery life at the present rate of discharge (minutes). the runtimetoempty value is calculated based on either current or power, depending on the setting of the batterymode ?s capacity_mode bit. this is an impor- tant distinction because use of the wrong calculation mode may result in inaccurate return values. 8.1.19 averagetimetoempty (0x12) returns a one-minute rolling average of the predicted remaining battery life (minutes). the averagetimetoempty value is calculated based on either current or power, depending on the setting of the batterymode ?s capacity_mode bit. this is an impor- tant distinction because use of the wrong calculation mode may result in inaccurate return values. 8.1.20 averagetimetofull (0x13) returns a one-minute rolling average of the predicted remaining time until the smart battery reaches full charge (minutes). 8.1.21 chargingcurrent (0x14) sets the maximum charging current for the smart charger to charge the battery. this can be written to the smart charger from the smart battery or requested by the smart charger from the battery. 8.1.22 chargingvoltage (0x15) sets the maximum charging voltage for the smart charger to charge the battery. this can be written to the smart charger from the smart battery or requested by the smart charger from the battery. 8.1.23 batterystatus (0x16) returns the smart battery?s status word (flags). some of the batterystatus flags, like remaining_capacity_alarm and remaining_time_alarm , are calculated based on either current or power, depending on the setting of the batterymode ?s capacity_mode bit. this is impor- tant because use of the wrong calculation mode may result in an inaccurate alarm. the batterystatus function is used by the power management system to get alarm and status bits, as well as error codes, from the smart battery. this is basically the same information returned by the sbdata alarmwarning function except that the alarmwarning function sets the error code bits all high before sending the data. also, information broadcasting is disabled in the ps501. battery status bits: bit 15: over_charged_alarm bit 14: terminate_charge_alarm bit 13: reserved bit 12: over_temp_alarm bit 11: terminate_discharge_alarm bit 10: reserved bit 9: remaining_capacity_alarm bit 8: remaining_time_alarm bit 7: initialized bit 6: discharging bit 5: fully_charged bit 4: fully_discharged the host system assumes responsibility for detecting and responding to smart battery alarms by reading the batterystatus to determine if any of the alarm bit flags are set. at a minimum, this requires the system to poll the smart battery batterystatus every 10 seconds at all times the smbus is active.
? 2004 microchip technology inc. ds21818b-page 23 ps501 8.1.24 cyclecount (0x17) cyclecount is updated to keep track of the total usage of the battery. cyclecount is increased whenever an amount of charge has been delivered to, or removed from, the battery equivalent to the full capacity. 8.1.25 designcapacity (0x18) returns the theoretical capacity of a new pack. the designcapacity value is expressed in either current or power, depending on the setting of the batterymode ?s capacity_mode bit. 8.1.26 designvoltage (0x19) returns the theoretical voltage of a new pack (mv). 8.1.27 specificationinfo (0x1a) returns the version number of the smart battery specification the battery pack supports. 8.1.28 manufacturedate (0x1b) this function returns the date the cell pack was manu- factured in a packed integer. the date is packed in the following fashion: (year-1980) * 512 + month * 32 + day. 8.1.29 serialnumber (0x1c) this function is used to return a serial number. this number, when combined with the manufacturername , the devicename and the manufacturedate , will uniquely identify the battery. 8.1.30 manufacturername (0x20) this function returns a character array containing the battery manufacturer?s name. 8.1.31 devicename (0x21) this function returns a character string that contains the battery?s name. 8.1.32 devicechemistry (0x22) this function returns a character string that contains the battery?s chemistry. for example, if the devicechemistry function returns ?nimh?, the battery pack would contain nickel metal hydride cells. the following is a partial list of chemistries and their expected abbreviations. these abbreviations are not case sensitive. lead acid: pbac lithium ion: lion nickel cadmium: nicd nickel metal hydride: nimh nickel zinc: nizn rechargeable alkaline-manganese: ram zinc air: znar 8.1.33 manufacturerdata (0x23) this function allows access to the manufacturer data contained in the battery (data). 8.1.34 optionalmfgfunction the ps501 includes new sbdata functions using the optionalmfgfunction command codes. the command codes, 3c hex to 3f hex, report the individual cell volt- ages as measured by the analog-to-digital converter. these voltages are reported in mv and are calculated to include compensation for calibration and sense resistance voltage drops. only one cell voltage is mea- sured per measurement cycle (depending on run or sample mode operation). rapid voltage changes will see some variation in volt- ages due to the delay of measurement. these voltage values may be used for cell balancing or other functions as the host system may desire.
ps501 ds21818b-page 24 ? 2004 microchip technology inc. table 8-2: ps501 alarms and status summary table 8-3: temperature , c harging c urrent ( ) and c harging v oltage ( ) summary for all other temperature conditions: chargingcurrent ( ) = chrgcurr chargingvoltage ( ) = chrgvolt battery status set condition clear condition fully_charged bit set at end-of-charge condition: charge fet off and any vc(x) input > 4.175v and iavg < eoc_iavg for chrgcntrltimer number of consecutive counts relativestateofcharge ( ) < clrfullychrg (default rsoc = 80%) over_charged_alarm bit v cell x > tcavolt (default 4.5v/cell) all v cell x < tcavolt terminate_charge_alarm bit v cell x > tcavolt (default 4.5v/cell) or charging temperature ( ) > chrgmaxtemp (default 60c) or fully_charged bit = 1 all v cell x < tcavolt and temperature ( ) < chrgmaxtemp and current ( ) = < 0 over_temp_alarm bit temperature ( ) > hightempal (default 55c) temperature ( ) < hightempal terminate_discharge_alarm bit primary method: v cell x < veod1 (per look-up table) and above condition continues for neareodrecheck time. secondary method: v cell x < veod2 (default 3.1v/cell) and above condition continues for eodrecheck time. primary method: all v cell x > veod1 or current ( ) > 0 secondary method: all v cell x > veod2 or current ( ) > 0 remaining_capacity_alarm bit remainingcapacity ( ) < remainingcapacityalarm ( ) remainingcapacity ( ) > remainingcapacityalarm ( ) remaining_time_alarm bit averagetimetoempty ( ) < remainingtimealarm ( ) averagetimetoempty ( ) > remainingtimealarm ( ) fully_discharged bit remainingcapacity ( ) = 0 relativestateofcharge ( ) > clrfullydischrg (default rsoc = 20%) temperature ( ) > hightempai (default 60c) charging discharging terminate_charge_alarm and o ver_temp_alarm over_temp_alarm cleared temperature ( ) < hightempai temperature ( ) > chrgmaxtemp (default 50c) temperature ( ) > dischrgmaxtemp (default 65c) charging discharging chargingcurrent ( ) = chrgcurroff chargingvoltage ( ) = chrgvoltoff temperature ( ) < chrgmintemp chargingcurrent ( ) = chrgcurroff chargingvoltage ( ) = chrgvolt
? 2004 microchip technology inc. ds21818b-page 25 ps501 9.0 parameter setup this section documents all of the programmable parameters that are resident in the eeprom. the parameter set is organized into the following functional groups: 1. pack information 2. capacity calculations 3. eod and fcc relearn 4. charge control 5. gpio 6. ps501 settings 7. sbdata settings 8. calibration table 9-1: pack information parameter name # bytes lower limit upper limit typical value operational description batstatus 1 0 255 b01000000 lower byte of sbdata register for batterystatus . cells 1 0 255 4 number of cells in the battery pack. chemistry 4 ? ? lion sbs data for chemistry. can be any ascii string. the chemistry name can be programmed here and retrieved with the sbdata devicechemistry command. date 2 0 65535 0x3042 sbdata value for manufacturedate . the date of manufacture of the battery pack can be programmed here and retrieved with the sbdata manufacturedate command. coding: date = (year-1980) x 512 + month x 32 + day designcapacity 2 0 65535 4400 sbdata value for designcapacity . this is the first capacity loaded into the fullchargecapacity upon power-up. designvpack 2 0 65535 14800 sbdata value for designvoltage . devicename 8 ? ? ps501 sbdata value for devicename . can be any ascii string. the battery circuit device name can be programmed here and retrieved with the sbdata devicename command. mfgdata 4 ? ? 0x0 sbs string for manufacturerdata . mfgname 10 ? ? microchip sbs string for manufacturername . can be any ascii string, typically the name of the battery pack manufacturer. length of string is defined by mfgnamelength . packres 2 0 65535 65 resistance of pack. pw1 2 0 65535 aa4d first password for the battery pack lock. pw2 2 0 65535 d4aa second password for the battery pack lock. specinfo 2 0 65535 33 specification info according to sbs spec. 0011, refers to smart battery specification version 1.1. serialnumber 2 0 65535 100 sbdata value for serialnumber . the serial number of the battery pack can be programmed here and retrieved with the sbdata serialnumber command.
ps501 ds21818b-page 26 ? 2004 microchip technology inc. table 9-2: capacity calculations parameter name # bytes lower limit upper limit typical value operational description currerror 1 0 255 1 current measurement error. this is the error due to the accuracy of the a/d converter to measure and integrate the current, 255 = 24.9%. cycles 2 0 65535 0 sbdata register for cyclecount . cycles is updated to keep track of the total usage of the battery. cycles is increased whenever an amount of charge has been delivered to or removed from the battery, equivalent to the full capacity. for a 4000 mah battery, cycles is increased every time 4000 mah goes through the battery terminals in any direction. initialcap 2 0 65535 2048 the initial capacity of the battery. when the ps501 is first powered up and initialized, before a learning cycle takes place to learn the full capacity, the full capacity will take the value programmed into initialcap to compute relative state-of-charge percentage. lowcurrerror 1 0 255 25 current offset for error calculation. since the error of the a/d converter is proportional to the level of current it is measuring, the error term can be too low when the current is very low. for this reason, the lowcurrerror will compensate the err term for low currents. lowcurrerror milli-amps are added to the current when factoring in the error. thus, the error is: error = (current + lowcurrerror ) * currerror . nchangestate 1 0 255 8 state change delay filter. delays the change between ?charge increasing? state and ?charge decreasing? state based on current direction. to avoid problems with current spikes in opposite directions, a delay filter is built-in to control when to change from charging status to discharging status. the current must change directions and stay in the new direction for cst_delay * period before the status is changed and capacity is increased or decreased as a result of the new current direction. nullcurr 1 0 255 3 a zero zone control is built into the ps501 so that any small inaccuracy doesn?t actually drain the gas gauge, when in fact the current is zero. for this reason, current less than nullcurr ma in either direction will be measured as zero. pwrconsumption 1 0 65535 140 current consumption of the battery module. this is the average current that the battery module typically draws from the battery (255 = 1 ma). selfdischrgerr 1 0 255 1 self-discharge error. this is the error inherent in the ability of the self-discharge look-up tables to meet actual battery characteristics, 255 = 100%.
? 2004 microchip technology inc. ds21818b-page 27 ps501 table 9-3: eod and fcc relearn parameter name # bytes lower limit upper limit typical value operational description adlnearempty 2 0 65535 3600 cell voltage at which a/d switches to emphasize voltage over current measurement near eod (mv). adlnearfull 2 0 65535 4000 cell voltage at which a/d switches to emphasize voltage over current measurement near eoc (mv). eod1cap 2 0 65535 150 the capacity that remains in the battery at veod1. this is typically a small amount used to power a shutdown sequence for the system. eod1voltage 2 0 65535 3100 voltage for eod1 fixed voltage point (mv). eod2recheck 1 0 255 6 delay filter for the eod2 condition. number of checks before eod2 trigger. the end-of-discharge conditions must remain for at least this number of periods before being con- sidered true, to help filter out false empty conditions due to spikes. eod2 condition is based on the variable voltage look-up table. fullcapacity 2 0 65535 4150 learned value of battery capacity. used for sbdata value of fullchargecapacity . this is a learned parameter which is the equivalent of all charge counted from fully charged to fully discharged, including self-discharge and error terms. this is reset after a learning cycle and used for remaining capacity and relative state-of-charge calculations. relearncurrlim 2 0 65535 10,000 value of measured current that prevents a capacity relearn from occurring when a terminate discharge alarm condition is reached at end-of-discharge (eod). a learning cycle will happen when the battery discharges from fully charged, all the way to fully discharged, with no charging in between and the discharge current never exceeds relearncurrlim (example: 3000). a relearn will only occur if current does not exceed 3000 ma. relearnlimit 1 0 255 205 the maximum relearn limit. the maximum percentage that the full_capacity can change after a learning cycle, where 255 = 100%. relearnmaxerr 2 0 65535 300 maximum error for learning fullcapacity . the full_capacity will not be learned after a learning cycle if the error is too great. rlcycles 1 0 255 2 the number of initial cycles without relearnlimit . the initial number of cycles where relearnlimit is not active. fullcapacity can vary more greatly with the first learning cycle since the initial capacity may not be correct, thus this should be set to at least ? 2 ?. vempty 2 0 65535 3000 second and final end-of-discharge voltage point. at this point, remaining capacity is optionally set to ? 0 ?.
ps501 ds21818b-page 28 ? 2004 microchip technology inc. table 9-4: charge control parameter name # bytes lower limit upper limit typical value operational description chrgcurr 2 0 65535 3000 this is the full charging current that the battery requires during normal charging. it can be broadcasted to the charger or read from the ps501. chrgcurroff 2 0 65535 0 trickle charging current. this is a small amount of current that the charger should deliver when full charging needs to be halted temporarily due to high temperature. chrgmaxtemp 1 0 255 235 temperature threshold when charging, coded value = (celsius * 10 + 200)/4. when the temperature exceeds chrgmaxtemp and the battery is charging, then chargingcurrent is set to chrgcurroff and chargingvoltage is set to chrgvoltoff . chrgmintemp 1 0 255 50 low temperature threshold, charging coded value = (celsius * 10 + 200)/4. when charging, if the temperature is less than chrgmintemp , then chargingcurrent is set to chrgcurroff and chargingvoltage is set to chrgvoltoff . chrgvolt 2 0 65535 16800 this is the voltage required by the battery during normal charging. chrgvoltoff 2 0 65535 16800 voltage required when charging should be halted. clrfullychrg 1 0 255 90 reset fully_charged bit at this level, 100 = 100%. once the fully_charged bit is set, taper or pulse current will not be monitored any more. when discharging begins, the fully_charged bit must remain set until the cell voltages are below eoc_volt so that a small current will not trigger a false end-of-charge trigger. thus, clrfullychrg is set at about 90%. fully_charged bit will be on until the battery has discharged to less than 90%. clrfullydischrg 1 0 255 10 reset fully_discharged bit, 100 = 100%. once fully discharged bit is set, it will stay set until capacity rises above this value, typically 10%. eoccuravg 2 0 65535 200 eoc trigger for pulse charging. if the average current during charging, with the cfet turned off, has dropped below the avgcurreocthresh threshold for a pass count equal to the eeprom parameter value chrgcntrltimr (typically between 8 and 16), the end-of-charge state will be reached. eocrecheck 1 0 255 6 delay filter for the eoc condition. number of checks before eoc trigger. the end-of-charge conditions must remain for at least this number of periods before being considered true, to help filter out false full conditions due to spikes. eocvolt 2 0 65535 4175 eoc trigger cell voltage. when any cell in the battery pack reaches this voltage, the end-of-charge determination will start monitoring the average current to determine when the battery is full. when the average current is in the proper range and the cell voltage is greater than eoc_volt, then fully_charged bit in batterystatus will be set and terminate charge alarm will be active. maxtemp 1 0 65535 750 maximum temperature measured (including external and internal sensor). coded value = (celsius * 10 + 200)/4. this is where the ps501 keeps track of the highest temperature it has measured. prechargecurr 2 0 65535 100 precharge current required. posted to sbdata chargingcurrent during precharge conditions.
? 2004 microchip technology inc. ds21818b-page 29 ps501 prechargemax 2 0 65535 500 maximum precharge current allowed. when exceeded under precharge conditions, sbdata chargingcurrent is set to zero. prechargetemp 1 0 255 60 precharge temperature, coded value = (celsius * 10 + 200)/4. this is the temperature under which precharging should occur. prechargevcell 2 0 65535 2500 precharge cell voltage. this is the voltage under which precharging should occur. socthreshold 1 0 255 125 second eoc trigger based on state-of-charge, 100 = 100%. a second end-of-charge trigger is built into the ps501, such that if the state-of-charge exceeds a certain value, end-of-charge will be forced, even if the taper or pulse current was not detected. when state-of-charge reaches socthreshold , then end-of-charge will trigger. stablecurr 1 0 255 50 eoc trigger current deviation level. in order to prevent current spikes from causing a premature taper current trig- ger, the average current and the instantaneous current must be within stablecurr of each other for the end-of-charge to trigger on the taper current. tapercrate 6 0 255 50 upper limit eoc taper current based on temperature, 256/28/ rfactor = 1c. taperlow 1 0 255 10 lower limit eoc taper current, 256/28/ rfactor = 1c. tapertemp 5 0 255 80 temperature corresponding to tapercrate byte. table 9-4: charge control (continued) parameter name # bytes lower limit upper limit typical value operational description
ps501 ds21818b-page 30 ? 2004 microchip technology inc. table 9-5: ps501 settings parameter name # bytes lower limit upper limit typical value operational description aomint 1 0 255 60 the frequency of the auto-offset calibration cycle. configeoc 1 0 255 b01101001 bit coded as follows: bit function 7 eoc on charge timer 6eoc on tcavolt 5 limit remcap to fcc 4 set overcharge alarm at eoc 3 load capacity with fcc at eoc 2 trigger eoc on rsoc > maxsoc 1 trigger eoc on average current 0 trigger eoc on taper current configeod 1 0 255 b01111000 bit coded as follows: bit function 7 evaluate eod1 on fixed voltage (else table) 6 set fully discharged bit on eod1 5 set capacity to residual capacity value immediately upon veod1 4 set terminate discharge alarm on veod1 (default on veod2) 3 learn fcc at veod1 2 tda alarm at eod2 1 set capacity to zero at veod2 0 do not allow capacity to drop below scap configcap 1 0 255 11010100 bit function 7 compensate remcap ? the displayed remcap actually equals fcc minus capacity used, minus residual capacity due to temperature. remcap is compensated for temperature. 6 remcap decrease only ? when compensating, if temperature changed causing a decrease in residual capacity, do not let remcap rise to reflect this. instead, hold it steady until discharge catches up. this is so user does not see capacity increase while discharging (though usable capacity may increase if the temperature changes, user would be confused). 5 use compensated fcc ? use compensated fcc to compute rsoc. allows compensated rsoc to equal 100% at full charge (delete). 4 limit rsoc to 99% until eoc. 3 report compensated fcc ? the compensated fcc is reported in sbdata to allow for externally calculated rsoc (delete). 2 set capacity to positive immediately upon charging. if discharged below zero, this allows capacity to count up immediately upon charging. 1 learn unconditionally ? relearn fcc no matter what. typically we have a max. current and a max. error limitation on relearn. this would take away the limitations. typically used for testing only. 0 self-discharge disable.
? 2004 microchip technology inc. ds21818b-page 31 ps501 configled 1 0 255 b10000010 bit coded as follows: bit function 7 disable master mode 6(free) 5 enable fast led time base 4 led display while charging 3 display the most significant led only 2 led using absolute soc, else relative soc 1 flash leds on remaining time or remaining cap alarm 0 flash leds while charging flags1 1 0 255 b11101011 bit coded as follows: bit function 7 enable precharge max current check 6 hold charge current = 0 until next discharge 5 int/ext temperature 4 disable sleep in main idle mode 3 require null current for low-voltage sleep mode 2 disable safety gpio 1 pack resistance enable 0 enable sample mode detect mwhconv 2 0 65535 2000 constant for conversion from mah to mwh. nsample 1 0 255 10 frequency of adc activity in sample mode. the a/d converter will take measurements every nsample period while in sample mode. in run mode, new measurements are taken every period. osctrim 1 0 255 200 rc oscillator trimming. samplelimit 2 0 65535 15 value used to determine the current threshold for entry/exit for sample and run modes in ma. smbmstrbaud 1 0 127 1 master broadcast baud rate (512 khz/4)/( smbmstrbaud + 1). smbchrgraddr 1 0 255 0x12 address to broadcast charger messages to. smbhostaddr 1 0 255 0x10 address to broadcast host messages to. smbalrminterval 1 0 255 120 delay between alarm broadcasts, units 0.5 seconds. config1 1 0 255 100 bootload configuration. sleepvpack 2 0 65535 8800 the pack voltage at which the ps501 will enter low-voltage sleep mode. wakeup 1 0 255 b00001011 when in the low-volt age sleep mode (entry due to low voltage and sample mode), there are four methods for waking up. they are voltage level, current level, smbus activity and i/o pin activity. this value defines which wake-up functions are enabled and also the voltage wake-up level. the table below indicates the appropriate setting. note that the setting is independent of the number of cells or their configuration. wake-up: bit name function 7 wakeio wake-up from i/o activity 6 wakebus wake-up from smbus activity 5 wakecurr wake-up from current 4 wakevolt wake-up from voltage 3 shelf-sleep use ultra low-power mode for shelf-sleep mode 1 lv sleep mode use ultra low-power mode as low-voltage sleep mode 0 zero remcap set remcap to zero when entering low-voltage sleep mode table 9-5: ps501 settings (continued) parameter name # bytes lower limit upper limit typical value operational description
ps501 ds21818b-page 32 ? 2004 microchip technology inc. table 9-6: sbdata settings wakelevels 1 0 255 b11000110 wake-up voltage: wakeup (2:0) voltage purpose 000 6.4v 2 cells li ion 001 6.66v 2 cells li ion 010 8.88v 2 cells li ion 011 9.6v 3 cells li ion 100 9.99v 3 cells li ion 101 11.1v 3 cells li ion 110 12.8v 4 cells li ion 111 13.3v 4 cells li ion wake-up current: wakeup (7:3) 00000 : minimum 11000 : typical recommended 11111 : maximum parameter name # bytes lower limit upper limit typical value operational description hightempal 1 0 255 200 over_temp_alarm threshold bit in alarmwarning register, 0.1c increments, coded value = (celsius * 10 + 200)/4. when the temperature exceeds hightempal , the over_temp_alarm becomes active. if charging, the terminate_charge_alarm also becomes active. nchrgbroadcast 1 0 255 20 frequency of charging condition broadcasts. remcapal 2 0 65535 440 sbdata value for remcapal . the sbdata specification requires a default of designcapacity /10 for this value. when the remaining capacity calculation reaches the value of remcapal , the remaining_capacity_alarm bit will be set in the batterystatus register and an alarm broadcast to the host will occur if alarm broadcasts are enabled. remtimeal 2 0 65535 10 sbdata value for remtimeal . sbdata requires a default of 10 minutes for this value. when the runtimetoempty calculation reaches the value of remtimeal , the remaining_time_alarm bit in the batterystatus register will be set. tcavolt 2 0 65535 4400 cell voltage when the battery sends terminate_charge_alarm. this is a voltage higher than the end-of-charge voltage that will trigger a terminate_charge_alarm in case eoc is not responded to by the charger. table 9-5: ps501 settings (continued) parameter name # bytes lower limit upper limit typical value operational description
? 2004 microchip technology inc. ds21818b-page 33 ps501 table 9-7: calibration parameter name # bytes lower limit upper limit typical value operational description calstatus 1 0 255 b10000000 bit coded as follows: bit function 7 factory calibrated 6 ee/flash downloaded 5 rc oscillator 4 external temperature 3 internal temperature 2 current 1 pack voltage 0 cell voltages 0 = not calibrated 1 = calibrated cfcurr 2 0 65535 6844 correction factor for current. adjusts the scaling of the sense resistor current measurements. used to calibrate the measurement of current at the rshp and rshn input pins. this is set for the size of the current sense resistor. cftempe 2 0 65535 1300 correction factor for temperature. adjusts the scaling of temperature measured across an external thermistor at the v ntc input pin. cftempi 2 0 65535 9102 correction factor for temperature. adjusts the scaling of temperature measured from the internal temperature sensor. calibration: new cf_temp = old cf_temp x (thermometer[c]/sbdata temperature [c] ) note: sbdata temperature is reported in 0.1k normally. it must be converted to c for this equation. cfvcell1 2 0 65535 22325 calibration correction factor for v cell 1. used to calibrate the measurement of individual cell voltage between the v cell 1-4 input pins. cfvcell2 2 0 65535 22393 calibration correction factor for v cell 2. used to calibrate the measurement of individual cell voltage between the v cell 1-4 input pins. cfvcell3 2 0 65535 22420 calibration correction factor for v cell 3. used to calibrate the measurement of individual cell voltage between the v cell 1-4 input pins. cfvcell4 2 0 65535 22470 calibration correction factor for v cell 4. used to calibrate the measurement of individual cell voltage between the v cell 1-4 input pins. cfvpack 2 0 65535 20045 correction factor for pack voltage. adjusts the scaling of the pack voltage measurements. used to calibrate the measurement of pack voltage between v cell 4 input pin and ground. cocurr 2 -32768 32767 -12 correction offset for current. this is the value the a/d reads when zero current is flowing through the sense resistor. cod 1 -128 127 -12 correction offset deviation. offset value for the auto-zero calibration of the current readings. sbdata current [ma] = (i_a/d ? co_curr ? cod) x cf_curr/16384 calibration: cf_curr = ((ammeter[ma] x 16384) ? 8192)/(current ? i_a/d at ocv)
ps501 ds21818b-page 34 ? 2004 microchip technology inc. cotempe 1 -128 127 -2 correction offset for temperature. offset = 0 used for temperature measurement using internal temperature sensor. cotempi 2 -32768 32767 21647 correction offset for temperature. offset = 0 used for temperature measurement using internal temperature sensor. covcell 1 -128 127 0 correction offset for cell voltage. offset factor used for individual cell voltage readings. sbdata voltage [mv] = (v_a/d ? co_volt) x cf_volt/2048 calibration: new cf_volt = old cf_volt x (voltmeter[mv]/sbdata voltage [mv]) covpack 1 -128 127 0 correction offset for voltage. offset factor used for pack voltage reading. bgcal 1 0 255 0 band gap voltage calibration factor. refcal 1 0 255 0 reference voltage calibration factor. vcellsafevolt 2 0 65535 4150 safe threshold for v cell s. samplemoderechecks 1 0 255 6 # of opcs current < samplelimit before entering sample mode. agefactor 1 0 255 0 scale factor for eod voltage due to aging. remcapdelta 1 0 255 1 maximum change in remaining capacity per measurement period. flags2 1 0 255 10000000 bit 7: 1 = compensate remcap only on discharge bit 6: internal test bit (cj) bit 5: internal test bit (cl) bit 4: compensate remcap on null current bit 3: unused bit 2: 1 = cell balancing enabled bit 1: 1 = compensate vc4/v pack bit 0: 1 = compensate vc1/v pack vcellmbset 1 0 255 100 voltage difference to trigger internal cell balancing. vcellmbreset 1 0 255 80 voltage difference to turn off cell balancing. pwruptimer 1 0 255 4 time during which gpio are inactive after first power-up. vc1res 2 0 65535 0 series resistance for v cell 1 measurement. 1/16384 ohms. vc4res 2 0 65535 0 series resistance for v cell 4 measurement. 1/16384 ohms. npermlogcnt 1 0 255 0 counter for logging faults. npermlogreg 1 0 255 0 register for logging faults. reinitgpio 2 0 65535 0 register for resetting all gpio during testing. gpiodelayflags 2 0 65535 0 positive logic change of gpio is delayed when upper byte is set. lower byte maps to gpio. gpiodelayms 1 0 255 0 gpio delay in milliseconds, when gpiodelayflags has the delay enabled. paramversion 1 0 255 0 eeprom version control number. keybyte 1 0 255 0xda ee keybyte must be 0xda before p5 will exit bootloader mode. eod1recheck 1 0 255 8 recheck period for eod. eoctimeout 2 0 65535 60 eoc time-out timer. caperrreset 2 0 65535 0 value to set m ax e rror to at eod. imbalancesoc 1 0 255 20 rsoc below which cell balance is measured. table 9-7: calibration (continued) parameter name # bytes lower limit upper limit typical value operational description
? 2004 microchip technology inc. ds21818b-page 35 ps501 10.0 electrical characteristics table 10-1: absolute maximum ratings symbol parameter min max units v cx voltage at any vc(x) pin -0.3 18.5 v v pin voltage directly at any pin (except v cell x) -0.5 7.0 v t bias temperature under bias -20 85 c t storage storage temperature (package dependent) -35 125 c note: these are stress ratings only. stress greater than the listed ratings may cause permanent damage to the device. exposure to absolute maximum ratings for an extended period may affect device reliability. functional operation is implied only at the listed operating conditions below. table 10-2: dc characteristics (t a = -20c to +85c; v reg (internal) = +3.3v 10%) symbol characteristic min typ max units condition v supply supply voltage ? applied to vc(1) 5.6 ? 18.0 v i dd instantaneous supply current ? 220 ? a (note 1) i ddrun average supply current ? run mode ? 175 ? a a/d active (note 1) i ddins inactive supply current ? sample mode ? 150 ? a a/d inactive (note 1, 2) i ddsslp inactive supply current ? low-power mode ? 25 ? a a/d inactive (note 1, 2) i ddslp average supply current ? ultra low-power mode ? 0.8 1 a sleep mode (note 1, 4) i wake wake-up current threshold from sleep mode ? (voltage across sense resistor) 2.50 3.75 5.00 mv v il input low voltage ? gpio(7-0) ? ? 0.2 * v ddd v v ih input high voltage ? gpio(7-0) 0.8 * v ddd ?? v i il - iopu gpio input low current ? pull-up mode -80 -110 -140 a i ih - iopd gpio input high current ? pull-down mode -80 -110 -140 a i l leakage current ? gpio pins programmed as outputs ?1 2 a v ol output low voltage for gpio(7-0) ? ? 0.6 v i ol = 0.5 ma v oh - io output high voltage for gpio(7-0) (non-led mode) 2.0 ? ? v i oh = 100 a v oh - led output high voltage for gpio(7-0) (led mode) 2.0 ? ? v i oh = 10 ma (note 3) v sr sense resistor input voltage range -152 ? 152 mv v ntc thermistor input voltage range 0 ? 152 mv v reft ntc reference voltage output at v reft pin ? 150 ? mv v il - smb input low voltage for smbus pins -0.5 ? 0.8 v v ih - smb input high voltage for smbus pins 2.0 ? 5.5 v v ol - smb output low voltage for smbus pins ? ? 0.4 v i pullup = 350 a v oh - smb output high voltage for smbus pins 2.1 ? 5.5 v i pullup - smb current through pull-up resistor or current source for smbus pins 100 ? 350 a i leak - smb input leakage current ? smbus pins ? ? 5 a note 1: does not include current consumption due to external loading on pins. valid for a maximum voltage of 16.8 volts for the referenced current specification. 2: sample mode current is specified during an a/d inactive cycle. sample mode average current can be calculated using the formula: average sample mode supply current = (i ddrun + (n ? 1) * i ddins )/n; where ?n? is the programmed sample rate. 3: during led illumination, currents may peak at 10 ma but average individual led current is typically 5 ma (using low-current, high-brightness devices). 4: measured at 25c.
ps501 ds21818b-page 36 ? 2004 microchip technology inc. table 10-3: ac characteristics (t a = -20c to +85c; v reg (internal) = +3.3v 10%) symbol characteristic min typ max units condition f rc internal rc oscillator frequency ? 512.000 ? khz f ad internal a/d clock frequency ? f rc /16 ? khz t conv a/d conversion measurement time, n-bit + sign ? 2 n /f ad ? ms table 10-4: ac characteristics ? smbus (t a = -20c to +85c; v reg (internal) = +3.3v 10%) symbol characteristic min typ max units condition f smb smbus clock operating frequency <1.0 ? 100 khz slave mode f smb - mas smbus clock operating frequency 50 f rc /8 68 khz master mode (note 1) t buf bus free time between start and stop 4.7 ? ? s t shld bus hold time after repeated start 4.0 ? ? s t su : sta setup time before repeated start 4.7 ? ? s t su : stop stop setup time 4.0 ? ? s t hld data hold time 300 ? ? s t setup data setup time 250 ? ? s t timeout clock low time-out period 10 ? 35 ms (note 2) t low clock low period 4.7 ? ? s t high clock high period 4.0 ? 50 s (note 3) t low : sext message buffering time ? ? 10 ms (note 4) t low : mext message buffering time ? ? 10 ms (note 5) t f clock/data fall time ? ? 300 ns (note 6) t r clock/data rise time ? ? 1000 ns (note 6) note 1: used when broadcasting alarmwarning , chargingcurrent and/or chargingvoltage values to either a smbus host or a smbus smart battery charger. this is only used when the ps501 becomes a smbus master for these functions. the receiving (slave) device may slow the transfer frequency. see smbus tutorial in p4 user?s guide for additional information. 2: the ps501 will time-out when the cumulative message time defined from start-to-ack, ack-to-ack or ack-to-stop exceeds the value of t timeout , min. of 25 ms. the ps501 will reset the communication no later than t timeout , max. of 35 ms. 3: t high max. provides a simple method for devices to detect bus idle conditions. 4: t low : sext is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to the stop. 5: t low : mext is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack or ack-to-stop. 6: rise and fall time is defined as follows: t r = (v il max -0.15) to (v ih min +0.15) t f = 0.9 v dd to (v il max -0.15)
? 2004 microchip technology inc. ds21818b-page 37 ps501 figure 10-1: smbus ac timing diagrams table 10-5: a/d converter characteristics (t a = -20c to +85c; v reg (internal) = +3.3v 10%) symbol characteristic min typ max units condition ad res a/d converter resolution 9 ? 16 bits (note 1) v adin a/d converter input voltage range (internal) 170 ? 170 mv differential mode 0 ? 340 mv single-ended mode e vgain supply voltage gain error ? ? 0.100 % e voffset compensated offset error ? ? 0.100 % e temp temperature gain error ? ? 0.100 % e inl integrated nonlinearity error ? ? 0.004 % note 1: voltage is internal at a/d converter inputs. v sr and v ntc are measured directly. vc(x) inputs are measured using internal level translation circuitry that scales the input voltage range appropriately for the converter. t hd:sta t buf t low t r t hd:sta t high t su:dat t f t su:sta t su:sta t su:sto p s s p scl sda scl sda t low:sext t low :mext t low:mext scl ack scl ack note: scl ack is the acknowledge related clock pulse generated by the master. t low:mext table 10-6: silicon time base characteristics (t a = -20c to +85c; v reg (internal) = +5.0v 10%) symbol characteristic min typ max units condition e time silicon time base error ? ? 0.35 % bias resistor r osc tolerance = 1%, t l = 100 ppm
ps501 ds21818b-page 38 ? 2004 microchip technology inc. 11.0 packaging information 11.1 mechanical packaging information 28-lead plastic shrink small outline (ss) ? 209 mil, 5.30 mm (ssop) * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-150 drawing no. c04-073 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 10.34 10.20 10.06 .407 .402 .396 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.10 7.85 7.59 .319 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.65 .026 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters* inches units 2 1 d p n b e1 e l c a2 a1 a significant characteristic
? 2004 microchip technology inc. ds21818b-page 39 ps501 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microc hip?s products as critical com- ponents in life support systems is not authorized except with express written approval by mi crochip. no licenses are con- veyed, implicitly or otherwis e, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, pic, picmicro, powersmart and smartshunt are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. smartsensor is a registered trademark of microchip technology incorporated in the u.s.a. powercal, powerinfo, powermate, powertool and smarttel are trademarks of microchip technology incorporated in the u.s.a. and other countries. all other trademarks mentioned he rein are property of their respective companies. ? 2004, microchip technology incorporated. printed in the u.s.a., all rights reserved. printed on recycled paper.
ds21818b-page 40 ? 2004 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: www.microchip.com atlanta 3780 mansell road, suite 130 alpharetta, ga 30022 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, in 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 san jose 1300 terra bella avenue mountain view, ca 94043 tel: 650-215-1444 fax: 650-961-0286 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing unit 706b wan tai bei hai bldg. no. 6 chaoyangmen bei str. beijing, 100027, china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu rm. 2401-2402, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-86766200 fax: 86-28-86766599 china - fuzhou unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - hong kong sar unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 china - shanghai room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen rm. 1812, 18/f, building a, united plaza no. 5022 binhe road, futian district shenzhen 518033, china tel: 86-755-82901380 fax: 86-755-8295-1393 china - shunde room 401, hongjian building, no. 2 fengxiangnan road, ronggui town, shunde district, foshan city, guangdong 528303, china tel: 86-757-28395507 fax: 86-757-28395571 china - qingdao rm. b505a, fullhope plaza, no. 12 hong kong central rd. qingdao 266071, china tel: 86-532-5027355 fax: 86-532-5027205 india divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-22290061 fax: 91-80-22290062 japan benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 singapore 200 middle road #07-02 prime centre singapore, 188980 tel: 65-6334-8870 fax: 65-6334-8850 taiwan kaohsiung branch 30f - 1 no. 8 min chuan 2nd road kaohsiung 806, taiwan tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan taiwan branch 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe austria durisolstrasse 2 a-4600 wels austria tel: 43-7242-2244-399 fax: 43-7242-2244-393 denmark regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45-4420-9895 fax: 45-4420-9910 france parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany steinheilstrasse 10 d-85737 ismaning, germany tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy via quasimodo, 12 20025 legnano (mi) milan, italy tel: 39-0331-742611 fax: 39-0331-466781 netherlands waegenburghtplein 4 nl-5152 jr, drunen, netherlands tel: 31-416-690399 fax: 31-416-690340 united kingdom 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44-118-921-5869 fax: 44-118-921-5820 05/28/04 w orldwide s ales and s ervice

▲Up To Search▲

Price & Availability of PS501-ISS

	To Download PS501-ISS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .